• Linux booting – 在u-boot引导linux kernel启动时，会进行kernel的解压，此时会涉及到内存的 频繁操作。所以如果能够成功引导启动，则能说明DDR能够正常读写。 DDR3 Issue分析 • 造成DDR3读写错误或者运行不稳定的可能有： – DDR3 EMIF4 寄存器配置不恰当(与对应的DDR3型号不符) – Custom board与Starterkit的layout相差比较大，TI默认设置的值无法 满足要求，需要重新做SW leveling – DDR3原理图设计有误 – DDR3走线存在问题：未按DATASHEET上的要求走线 调试例子 • 问题描述：系统能够正常boot，当Linux启动后，运行LCD测试程序会导致系统 crash，且出现频率较高，能复现。 • 查看要点： a)是否做过SW leveling b)检查 DDR3的timing and EMIF registers设置是否与对应的DDR3型号匹配 c) 检查 DDR3的原理图设计是否有问题 d)检查DDR3的PCB layout 是否有问题 e)使用示波器查看关键信号，分析信号完整性 • 问题原因：查看DDR3布线，发现LCD的数据线走在DDR3的keepout 区域内， 且与DDR3数据线距离十分近。 Backup Questions • How to do single-ended termination for DQS and DQ?
SDRAM termination • ZQ calibration： is intended to control the ODT values and output drivers (Rtt and Ron respectively) of the SDRAM. ZQ calibration is not a controllable feature from the DSP. It is controlled using a precision (1% tolerance) 240 resistor. • ODT： In DDR3, the AM335 controller ODT pins (connected to each SDRAM) serve to turn on or off the SDRAM internal termination. The actual ODT functionality of each SDRAM is controlled using the mode registers (see the respective SDRAM data sheets for additional information). – reg_dyn_odt is the dynamic ODT enable/disable feature available in DDR3. • SDRAM_CONFIG: – reg_ddr_term is the termination on the DDR. It is used to enable parallel termination on the DDR memory when a WRITE command is issued. ODT on DDR3 DDR controller termination • ddr_data0_ioctrl & ddr_data1_ioctrl Register – io_config_i：3-bit configuration input to program data IO output impedance. – io_config_i_clk：3-bit configuration input to program clock IO pads(DDR_DQS/DDR_DQSn) output impedance. – io_config_sr：2 bit to program data IO Pads output slew rate. – io_config_sr_clk： 2 bit to program clock IO Pads (DDR_DQS/DDR_DQSn) output slew rate. • DDR_PHY_CTRL_1 Register Leveling • Read Leveling The memory controller also automatically corrects for delay skew between SDRAMs during Read Leveling. Read Leveling takes advantage of values loaded into the SDRAMs multi-purposed register (MPR). The values loaded into this register are used by the DDR3 controller to calibrate each signal path relative to skew. Each respective SDRAM byte is then internally corrected thus improving performance. • Write Leveling The memory controller automatically corrects for delay skew between SDRAMs during Write Leveling. During Write Leveling, correction for SDRAM skew (the tDQSS, tDSS and tDSH) is handled using a programmable DQS delay to shore up the timing relationship to the clock and strobe signals. During the Write Leveling procedure the DDR3 controller will delay the DQS until a valid change of state is detected at the SDRAM clock (CK) signal. DDR3 Topology
